Among numerous silicon transistor technologies, previous methods are known for forming, for example, a well of N-conductivity type in a semiconductor substrate of P-conductivity type, and another well of P-conductivity type is formed in the well of N-conductivity type. These portions are hereinafter referred to as N-well, P-substrate and P-well, respectively.
The thus formed structure, having a well incorporating therein a further well of the opposite conductivity type, is called a ‘triple well’ or ‘double well’, as the third well after the P-well and N-well.
In the triple well structure, the outer well is often called in general as a ‘deep P-well’ or ‘deep N-well’, and the inner well as a ‘IP-well’ or ‘IN-well’, which are herein adopted in the following description. It may be added that a P-well and an N-well alone included in the structure is called as a ‘twin well’.
Also in the following description, the term ‘normal P-well’ is applied to the P-well for forming therein an N-channel MOS transistor (or insulated gate field-effect transistor) which is hereinafter referred to as Nch transistor, and the term ‘normal N-well’ to the N-well for forming therein a P-channel MOS transistor which is referred to as Pch transistor, hereinafter.
FIG. 22 is a cross-sectional view illustrating the well structure of a known semiconductor device including a triple well.
Referring to FIG. 22, a conventional triple well is formed by first forming a deep N-well (DNW) 103 in a P-substrate 101, and further forming an IP well (IPW) 105 in the deep N-well 103 in a manner electrically isolated from the deep N-well, a triple well is formed. Also formed in the substrate 101 are a normal N-well (NW) 107 and a normal P-well (PW) 109.
In addition, by forming further transistors in the wells of FIG. 22, a semiconductor device of FIG. 23 is formed.
Namely, a LOCOS oxide layer 111 is first formed on the surface of the P-substrate 101 by the LOCOS (local oxidation of silicon) method for isolating the deep N-well 103, normal N-well 107 and normal P-well 109 from each other.
In the region for forming the IP well 105, an Nch transistor 113 is then formed consisting of a source (N+) 113s, a drain (N+) 113d and a gate electrode 113g, in which the source 113s and drain 113d are each formed of high concentration N-type diffusion layers spatially separated from one another, and which the gate electrode 113g of a polysilicon layer is formed over the IP well 105 between the source 113s and drain 113d incorporating an underlying gate oxide layer 113ox. 
In addition, a normal Pch transistor 115 is formed in the normal N-well 107 consisting of a source (P+) 115s, a drain (P+) 115d and a gate electrode 115g, in which the source 115s and drain 115d are each formed of P-type diffusion layers spatially separated from one another, and which the gate electrode 115g of a polysilicon layer is formed over the N-well 107 between the source 115s and drain 115d incorporating an underlying gate oxide layer 115ox. 
Further, in the region for forming the P well 109, a normal Nch transistor 117 is formed consisting of a source (N+) 117s, a drain (N+) 117d and a gate electrode 117g, in which the source 117s and drain 117d are each formed of high concentration N-type diffusion layers spatially separated from one another, and which the gate electrode 117g of a polysilicon layer is formed over the P-well 109 between the source 117s and drain 117d incorporating an underlying gate oxide layer 117ox. 
A CMOS (complementary MOS) logical circuit 119 is then formed with the thus formed Pch transistor 115 and Nch transistor 117.
The Nch transistor 113 of FIG. 23 is formed incorporating therein the above noted triple well structure, further including the CMOS logical circuit 119. It may be noted the triple well structure has been attracting much attention as will be described later on.
The inclusion of the triple well structure offers several advantages which follows:    (1) Since the IP well is electrically isolated from the P-substrate, voltage values applied to the IP well can arbitrarily be adjusted, whereby the degree of freedom in circuit design increases. This is in contrast to the conventional transistor structure, in which the voltage value applied to the IP well is limited to zero potential (GRD), since its IP well is generally connected to the substrate.    (2) Since even negative voltages can be applied to the IP well, negative voltages can be handled in the circuit and the incorporation of a negative voltage source becomes feasible.    (3) The deep N-well functions effectively to absorb noise components transmitted through the P-substrate. By forming a noise sensitive circuit such as, for example, an amplifier in the IP well, therefore, high precision circuits can be attained. In addition, the on-chip fabrication of DC/DC converter also becomes feasible, which has been practically impossible because of the noise problems.    (4) Since the deep N-well also functions effectively to absorb electrons generated in the vicinity thereof, data destruction such as soft error caused, for example, in DRAM (dynamic random access memory) can be prevented.
FIGS. 24A through 24E are each cross sectional views generally illustrating process sequence for fabricating the semiconductor device of FIG. 23.
Referring to FIGS. 23 through 24E, the fabrication process steps will be described herein below.    (1) By photolithographic techniques, a photoresist pattern is formed on a P-substrate 101 for defining the region for forming a deep N-well. Using the photoresist pattern as a mask for ion implantation, phosphorus ions are implanted under the conditions of an acceleration energy of 160 keV and a dose of approximately 2×1013 cm−2. The implanted phosphorus ions are then subjected to thermal diffusion at 1150° C. for 10 hours in gaseous nitrogen atmosphere, whereby the deep N-well 103 is formed. The photoresist pattern is subsequently removed (FIG. 24A).    (2) Also by photolithographic techniques, a further photoresist pattern is formed on the P-substrate 101 for defining the region for forming an N-well. Using the photoresist pattern as a mask for implantation, phosphorus ions are implanted under the conditions of an acceleration energy of 160 keV and a dose of approximately 2×1013 cm−2. The implanted phosphorus ions are then subjected to thermal diffusion at 1150° C. for 2 hours in gaseous nitrogen atmosphere, whereby the normal N-well 107 is formed. The photoresist pattern is subsequently removed (FIG. 24B).    (3) By photolithographic techniques, a photoresist pattern is formed so on the P-substrate 101 for defining the region for forming a normal P-well. Using the photoresist pattern as a mask for implantation, boron ions are implanted under the conditions of an acceleration energy of 30 keV and a dose of approximately 1×1013 cm−2. The implanted boron ions are then subjected to thermal diffusion at 1150° C. for 1 hour in gaseous nitrogen atmosphere, whereby the normal P-well 109 is formed. The photoresist pattern is subsequently removed (FIG. 24G).    (4) A photoresist pattern is formed also by photolithographic techniques on the P-substrate 101 for defining the region for forming an IP well having an opening on the portion of the deep N-well region. Using the photoresist pattern as a ask for ion implantation, boron ions are implanted under the conditions of an acceleration energy of 30 keV and a dose of approximately 3×1013 cm−2. The implanted boron ions are then subjected to thermal diffusion at 1150° C. for 1 hour in gaseous nitrogen atmosphere, whereby the IP well 105 is formed in the deep N-well region. The photoresist pattern is subsequently removed (FIG. 24D).    (5) By the LOCOS method, a LOCOS oxide layer 111 for device isolation is formed on the P-substrate 101. This LOCOS oxide layer is formed by depositing a layer of silicon nitride to a thickness of 100 nm over the entire surface of the structure carrying out photolithographic process steps for defining the device isolation region as an opening, and removing the silicon nitride layer by etching from the opening region. Thereafter, the thus prepared structure is subjected to wet oxidation steps at 1000° C. for 2 hours, whereby the LOCOS oxide layer 111 is formed in the opening region to a thickness of 500 nm (FIG. 24E).
Subsequently, by conventional transistor fabrication techniques, gate oxide layers 113ox, 115ox and 117ox, gate electrodes 113g, 115g and 117g, sources 113s, 115s and 117s, and drains 113d, 115d and 117d, are then formed respectively, whereby the structure shown in FIG. 23 is formed.
The above description on the triple well has been made rather briefly in general. Therefore, details of the process can be modified if necessary. In the process sequence, for example, the step for forming the normal N-well 107 may be interchanged with that of normal P-well 109, still arriving at the same final structure as FIG. 22.
As a further constituent for forming the present semiconductor device, a LOCOS offset transistor is adopted (for example, Japanese Laid-Open Patent Application No. 6-334129).
Like the aforementioned triple well structure, the LOCOS offset transistor has also been quite noticeable recently, as one of dispensable components for forming high voltage devices for its suitable high withstand voltage characteristics.
In a similar manner to conventional CMOS transistors, there are two types of LOCOS offset transistor, Nch and Pch, and they are typically shown in FIG. 25.
In the P-substrate, an N-well (NW) 121 and a P-well are formed in the regions for forming a LOCOS offset Pch transistor 131 and a LOCOS offset Nch transistor 123, respectively. The N-well (NW) 121 and a P-well (PW) 123 are separated from one another by a LOCOS oxide layer 111.
There formed in the N-well 121 are a source (P+) 129s of high concentration P-type diffusion layer and a low concentration P-type diffusion layer (P−) 125 of a concentration lower than the high concentration P-type diffusion layer, being spatially separated from one another.
A drain (P+) 129d is formed of a high concentration P-type diffusion layer having a concentration higher than the low concentration P-type diffusion layer 125, in the low concentration P-type diffusion layer 125 and spatially separated from the edge portion of the low concentration P-type diffusion layer 125 on the side of the source 129s. 
A drain of the LOCOS offset Pch transistor 129 is thus formed of the low concentration P-type diffusion layer 125 and drain 129d. 
In addition, a LOCOS oxide layer 111a is formed on the surface of P-type diffusion layer 125 partially overlapped with the drain 129d and spatially separated from the edge portion of low concentration P-type diffusion layer 125 toward the source 129s. The LOCOS oxide layer 111a is herein formed simultaneously with the LOCOS oxide layer 111 at the same stage of forming process.
A gate electrode 129g of a polysilicon layer is formed on the thus prepared structure, extending from the edge portion of the source 129s on the side of the LOCOS oxide layer 111a through the upper face portion of LOCOS oxide layer 111a by way of the upper face portion of the N-well 121 between the source 129s and low concentration P-type diffusion layer 125.
The gate electrode 129g is provided over the source 129s, N-well 121 and low concentration P-type diffusion layer 125 incorporating an underlying gate oxide layer 129ox. 
There formed in the N-well 123 are a source (N+) 131s of high concentration P-type diffusion layer and a low concentration N-type diffusion layer (NW) 127 of a concentration lower than the high concentration N-type diffusion layer, being spatially separated from one another.
A drain (N+) 131d is formed of a high concentration N-type diffusion layer having a concentration higher than the low concentration N-type diffusion layer 127, in the low concentration N-type diffusion layer 127 and spatially separated from the edge portion of the low concentration N-type diffusion layer 127 toward the source 131s. 
A drain of the LOCOS offset Nch transistor 131 is thus formed of the drain 131d and low concentration N-type diffusion layer 127.
In addition, a LOCOS oxide layer 111b is formed on the surface of N-type diffusion layer 127 partially overlapped with the drain 131d and spatially separated from the edge portion of low concentration N-type diffusion layer 127 toward the source 131s. The LOCOS oxide layer 111b is herein formed simultaneously with the LOCOS oxide layers, 111 and 111a, at the same stage of forming process.
A gate electrode 131g of a polysilicon layer is formed on the thus prepared structure, extending from the edge portion of the source 131s on the side of the LOCOS oxide layer 111b through the upper face portion of LOCOS oxide layer 111b by way of the upper face portion of the P-well 123 between the source 131s and low concentration N-type diffusion layer 127.
The gate electrode 131g is provided over the source 131s, P-well 123 and low concentration N-type diffusion layer 127 incorporating an underlying gate oxide layer 131ox. 
The structural characteristics of the LOCOS offset transistors are summarized in the following two points.
(1) The drain accompanies the surrounding low concentration N-type diffusion layer. That is, referring to FIG. 25, the drain 129d is surrounded by the low concentration P-type diffusion layer 125 in the LOCOS offset Pch transistor 129, and the drain 131d is surrounded by the low concentration N-type diffusion layer 127 in the LOCOS offset Nch transistor 131.
(2) The gate electrode climbs over the LOCOS oxide layer on the side of the drain. That is, referring again to FIG. 25, the gate electrode 129g is formed, in the LOCOS offset Pch transistor 129, extending from the portion partially overlying the edge of the source 129s on the side of the LOCOS oxide layer 11a to the upper face portion of LOCOS oxide layer 111a; and the gate electrode 131g is formed, in the LOCOS offset Nch transistor 131, extending from the portion partially overlying the edge of the source 131s on the side of the LOCOS oxide layer 111b to the upper face portion of LOCOS oxide layer 111b. 
Owning to the above noted structural characteristics, the LOCOS offset transistors can achieve high withstand voltage capabilities, which detailed herein below in reference to FIG. 26.
FIG. 26 is a cross sectional view illustrating the LOCOS offset Nch transistor and a normal Nch transistor. As mentioned earlier, by the normal transistor is meant one neither the LOCOS offset transistor nor the transistor formed in either IP well or IN well.
Since the LOCOS offset Nch transistor and Nch transistor have each the same structure as the offset transistor 131 of FIG. 25 and the Nch transistor 117 of FIG. 23, respectively, the detailed description on their structure is herein abbreviated. In addition, while the conductivity type is herein assumed to be N-type, a similar description can be made on P-type devices, as well.
When the drain 117d in the LOCOS offset Nch transistor 117 is examined closely, the withstand voltage thereof is determined by the avalanche breakdown voltage of the PN junction between the normal P-well 10 and drain 117d. Since the drain 117d has a high impurity concentration and is directly in contact with the normal P-well 109 in the present case, its withstand voltage is obtained ranging from 10 to 15 V.
In contrast, the drain 131d in the LOCOS offset Nch transistor 131 is surrounded by the low concentration N-type diffusion layer 127, and the high concentration drain 131d is not in direct contact with the P-well 123. As a result, the avalanche breakdown voltage of the PN junction between the drain 131d and N-type diffusion layer 127 increases ranging from 30 to 40 V.
On the other hand, it is known, when the gate electrode is fixed at the GND potential, the withstand voltage of the PN junction directly under a gate electrode decreases, which is called the gate modulated withstand voltage.
As a result, when the gate electrode 117g is at th GND potential, the portion in the vicinity of the drain 117d, which is shown a encircled portion in FIG. 26, is subjected to the at a voltage as low as approximately 10 V.
In the LOCOS offset Nch transistor 131, in contrast, the LOCOS oxide layer 111b is formed under the gate electrode 131g on the side of the drain 131d, and accordingly the distance between the edge portion of the gate electrode 131g on the side of the drain 131d and the portion of PN junction formed between the P-well 123 and low concentration N-type diffusion layer 127 is increased.
As a result, the gate modulated withstand voltage for the drain 131d is increased ranging from 30 to 40 V.
Summarizing the above results, this increase in the withstand voltage in LOCOS offset Pch transistor is therefore achieved by the structural characteristics mentioned earlier, that is, (1) the drain surrounded by the low concentration N-type diffusion layer, and (2) the gate electrode climbing over the LOCOS oxide layer on the side of the drain.
FIGS. 27A through 27D are each cross sectional views generally illustrating process sequence for fabricating the semiconductor device of FIG. 25.
Referring to FIGS. 25 through 27D, the fabrication process steps will be described herein below.
(1) By photolithographic techniques, a photoresist pattern is formed on a P-substrate 101 for defining the region for forming an N-well. Using the photoresist pattern as a mask for ion implantation, phosphorus ions are implanted under the conditions of an acceleration energy of 160 keV and a dose of approximately 2×1013 cm−2. The implanted phosphorus ions are then subjected to thermal diffusion at 1150° C. for 2 hours in gaseous nitrogen atmosphere, whereby the N-well 121 is formed. The photoresist pattern is subsequently removed.
Also by photolithographic techniques, another photoresist pattern is formed on the P-substrate 101 for defining the region for forming a P-well. Using the photoresist pattern as a mask for implantation, boron ions are implanted under the conditions of an acceleration energy of 30 keV and a dose of approximately 1×1013 cm−2. The implanted boron ions are then subjected to thermal diffusion at 1150° C. for 1 hour in gaseous nitrogen atmosphere, whereby the P-well 123 is formed. The photoresist pattern is subsequently removed (FIG. 27A).
(2) A photoresist pattern is formed also by photolithographic techniques on the P-substrate 101 for defining the region for forming a low concentration N-type diffusion layer having an opening on the portion of the P-well region. Using the photoresist pattern as a mask for ion implantation, phosphorus ions are implanted under the conditions of an acceleration energy of 100 keV and a dose of approximately 2×1013 cm−2. The photoresist pattern is subsequently removed.
Another photoresist pattern is formed also by photolithographic techniques on the P-substrate 101 for defining the region for forming a low concentration P-type diffusion layer having an opening on the portion of the N-well region. Using the photoresist pattern as a mask for ion implantation, boron ions are implanted under the conditions of an acceleration energy of 100 keV and a dose of approximately 5×1013 cm−2.
The boron ions implanted into N-well 121 and phosphorus ions implanted into the P-well 123 are then subjected to thermal diffusion at 1000° C. for 20 minutes in gaseous nitrogen atmosphere, whereby the low concentration N-type diffusion layer 127 and low concentration P-type diffusion layer 125 are formed in the P-well 123 and N-well 121, respectively. Thereafter, the photoresist pattern for defining the low concentration P-type diffusion layer is removed (FIG. 27B).
It is noted in this context that photolithographic process steps for each the low concentration N-type diffusion layer 127 and the low concentration P-type diffusion layer are separately required.
(3) By the LOCOS method, the LOCOS oxide layers 111, 111a and 111b are formed on the P-substrate 101 simultaneously. These LOCOS oxide layers are formed by first carrying out photolithographic process steps for defining the regions for forming LOCOS oxide layers, and subsequently subjecting these regions to wet oxidation steps at 1000° C. for 2 hours. The LOCOS oxide layers 111 are herein formed on respective device isolation regions, while the LOCOS oxide layers, 111a and 111b are formed on the surface of the low concentration P-type diffusion layer 125 and N-type diffusion layer 127, respectively (FIG. 27C).
(4) A layer of silicon oxide for forming gate oxide layers is formed on the surface of the structure on the P-substrate 101 to a thickness of 30 nm. Thereafter, a layer of polysilicon is deposited to a thickness of 300 nm on the entire surface of the P-substrate 101 at 600° C. by the low pressure CVD (chemical vapor deposition) method. After doping the polysilicon layer with phosphorus ions to reduce its resistively, a photoresist pattern is formed for defining gate electrodes by photolithographic techniques. Using the photoresist pattern as a mask, patterning steps of the polysilicon layer are carried out by anisotropic plasma etching techniques in gaseous hydrogen bromide, whereby gate electrodes 129g and 131g are formed (FIG. 27D). It may be is noted the layers of silicon oxide formed during the above process steps other than the gate oxide layers 129ox and 131ox are excluded in FIG. 27D for reasons of clarity.
(5) By implanting either boron ions or BF3 into the N-well 121 and low concentration P-type diffusion layer 125 using the ion implantation techniques, a P-type source 129s and drain 131d are formed. Also, by implanting either phosphorus or arsenic ions into the P-well 123 and low concentration N-type diffusion layer 127, an N-type source 131s and drain 131d are formed. A LOCOS offset Pch transistor 129 and LOCOS offset Nch transistor 131 are thereby formed, respectively (FIG. 25).
The process steps were described herein above on the triple well and the LOCOS offset transistor in reference to FIGS. 23 through 24E and FIGS. 25 through 27D, respectively.
These devices are quite different from one another in function and operation, and have been fabricated separately on each individual chip. The trend of fabrication has changed recently, however, with increasing demands toward higher device capabilities, higher degree of integration, and the reduction in chip area, among others.
Namely, there has given rise to the demand for forming both triple well and LOCOS offset transistor on the same chip. This is typically exemplified by the formation on a single chip of both a negative voltage source with the triple well structure and a high withstand voltage circuit with the LOCOS offset transistor.
FIG. 28 is a cross-sectional view illustrating a known semiconductor device including a triple well, LOCOS offset transistor and CMOS logic circuit.
Referring to FIG. 28, there formed in a P-substrate 101 are a deep N-well 103, normal N-well 107 and P-well 123, being isolated from each other by LOCOS oxide layer 111. In addition, an IP well 105 is formed in the deep N-well 103.
Also formed are an Nch transistor 113 in the IP well 105, a normal Pch transistor 115 in the normal N-well 107, and normal Nch transistor 117 in the P well 109. The Nch transistor 113, normal Pch transistor 115 and normal Nch transistor 117 each have the same structure as shown in FIG. 23.
Additionally formed are a LOCOS offset Pch transistor 129 in the N-well 121 and LOCOS offset Nch transistor 131 in the P-well 123. The LOCOS offset Pch transistor 129 and LOCOS offset Nch transistor 131 each have the same structure as shown in FIG. 25.
Furthermore, the fabrication steps for the present semiconductor device are described as the combination of the steps for forming the triple well described earlier in reference to FIGS. 23 through 24E, and ones for forming the LOCOS offset Pch transistor described in reference to FIGS. 25 through 27D.
FIGS. 29A through 29G are each cross sectional views generally illustrating process sequence for fabricating the semiconductor device of FIG. 28.
Referring to FIGS. 28 through 29G, the fabrication process steps will be described herein below.
(1) By photolithographic techniques, a photoresist pattern is formed on a P-substrate 101 for defining the region for forming a deep N-well 103. Using the photoresist pattern as a mask for ion implantation, phosphorus ions are implanted under the conditions of an acceleration energy of 160 keV and a dose of approximately 2×1013 cm−2. The implanted phosphorus ions are then subjected to thermal diffusion at 1150° C. for 10 hours in gaseous nitrogen atmosphere, whereby the deep N-well 103 is formed in the region for forming Nch transistor 113. The photoresist pattern is subsequently removed (FIG. 29A).
(2) Also by photolithographic techniques, another photoresist pattern is formed on the P-substrate 101 for defining a normal N-well 107 and N-well 121. Using the photoresist pattern as a mask for ion implantation, phosphorus ions are implanted under the conditions of an acceleration energy of 160 keV and a dose of approximately 2×1013 cm−2. The implanted phosphorus ions are then subjected to thermal diffusion at 1150° C. for 2 hours in gaseous nitrogen atmosphere, whereby the normal N-well 107 and N-well 121 are formed in the regions for forming a LOCOS offset Pch transistor 115 and a LOCOS offset Nch transistor 131, respectively. The photoresist pattern is subsequently removed (FIG. 29B).
(3) Still another photoresist pattern is formed also by photolithographic techniques on the P-substrate 101 for defining the regions for forming a normal P-well 109 and P-well 125. Using the photoresist pattern as a mask for implantation, boron ions are implanted under the conditions of an acceleration energy of 30 keV and a dose of approximately 1×1013 cm−2. The implanted boron ions are then subjected to thermal diffusion at 1150° C. for 1 hour in gaseous nitrogen atmosphere, whereby the normal P-well 109 and P-well 125 are formed in the regions for forming a normal Nch transistor 117 and the LOCOS offset Nch transistor 131, respectively. The photoresist pattern is subsequently removed (FIG. 29C).
(4) A photoresist pattern is formed also by photolithographic techniques on the P-substrate 101 for defining the region for forming an IP well having an opening on the portion of the region of the deep N-well 103. Using the photoresist pattern as a mask for ion implantation, boron ions are implanted under the conditions of an acceleration energy of 30 keV and a dose of approximately 3×1013 cm−2. The implanted boron ions are then subjected to thermal diffusion at 1150° C. for 1 hour in gaseous nitrogen atmosphere, whereby the IP well 105 is formed in the deep N-well 103. The photoresist pattern is subsequently removed (FIG. 29D).
(5) A photoresist pattern is formed by photolithographic techniques on the P-substrate 101 for defining the region for forming a low concentration N-type diffusion layer 127 having an opening on the portion of the region of the P-well 125. Using the photoresist pattern as a mask for ion implantation, phosphorus ions are implanted under the conditions of an acceleration energy of 100 keV and a dose of approximately 3×1013 cm−2.
Another photoresist pattern is formed by photolithographic techniques on the P-substrate 101 for defining the region for forming a low concentration P-type diffusion layer 123 having an opening on the portion of the region of the N-well 121. Using the photoresist pattern as a mask for ion implantation, boron ions are implanted under the conditions of an acceleration energy of 100 keV and a dose of approximately 3×1013 cm−2.
The boron ions implanted into N-well 121 and phosphorus ions implanted into the P-well 125 are then subjected to thermal diffusion at 1000° C. for 20 minutes in gaseous nitrogen atmosphere, whereby the low concentration P-type diffusion layer 123 and low concentration N-type diffusion layer 127 are formed in the N-well 121 and P-well 125, respectively. Thereafter, the photoresist pattern for defining the low concentration P-type diffusion layer 123 is removed (FIG. 29E).
Therefore, for forming the low concentration P-type diffusion layer 123 and low concentration N-type diffusion layer 127, there required are two photolithographic steps, the one for defining the region for forming the low concentration P-type diffusion layer 123 and the other for defining the region for forming the low concentration N-type diffusion layer 127; and additional two ion implantation steps.
(6) By the LOCOS method, the LOCOS oxide layers 111, 111a and 111b are formed on the P-substrate 101 simultaneously. These LOCOS oxide layers are formed by first carrying out photolithographic process steps for defining the LOCOS oxide layers including ones for device isolation, and subsequently subjecting these layers to wet oxidation steps at 1150° C. for 2 hours. The LOCOS oxide layers 111 are herein formed on respective device isolation regions, while the LOCOS oxide layers, 111a and 111b, are formed on the surfaces of low concentration P-type diffusion layer 123 and N-type diffusion layer 127, respectively (FIG. 29E).
(7) Thereafter, gate oxide layers 113ox, 115ox, 117ox, 129ox and 131ox are each formed on the P-substrate 101 to a thickness of 30 nm. Subsequently, a layer of polysilicon is deposited to a thickness of 300 nm on the entire surface of the P-substrate 101 at 600° C. by the low pressure CVD (chemical vapor deposition) method. After doping the polysilicon layer with phosphorus ions to reduce its resistively, a photoresist pattern is formed for defining gate electrodes by photolithographic techniques. Using the photoresist pattern as a mask, patterning steps of the polysilicon layer are carried out by anisotropic plasma etching techniques in gaseous hydrogen bromide, whereby gate electrodes 113g, 115g, 117g, 129g and 131g are formed (FIG. 29G).
It may be is noted the layers of silicon oxide formed during the above process steps other than the gate oxide layers 113ox, 115ox, 117ox, 129ox and 131ox are excluded in FIG. 29G for reasons of clarity.
(8) By implanting either phosphorus or arsenic ions into the IP-well 109, 125 and low concentration N-type diffusion layer 127, N-type sources 113s, 117s and 131s, and drains 113d, 117d and 131d are formed. Also, by implanting either boron ions or BF3 into the N-well 121, normal N-well 107 and low concentration P-type diffusion layer 123 using the ion implantation techniques, P-type sources 115s and 129s, and drains 115d and 129d are formed. A LOCOS offset Pch transistor 129 and LOCOS offset Nch transistor 131 are thereby formed, respectively (FIG. 25).
As a result, the Nch transistor 113 in the triple well, the Pch transistor 115 and Nch transistor 117 for constituting a CMOS logic 119, the LOCOS offset Pch transistor 129, and LOCOS offset Nch transistor 131, are able to simultaneously be formed respectively (FIG. 28).
For forming the triple well and LOCOS offset Nch transistors simultaneously, therefore, a relatively large number of photolithographic process have been required previously.
On taking count of the photolithographic steps described herein above in reference to FIGS. 29A through 29G, these required steps are the first photolithography process step for forming the deep N-well 103; the second step for forming the N-well 121, the deep N-well 103; the third step for forming the P-well 125; the fourth step for forming the IP well 105; the fifth step for forming the low concentration N-type diffusion layer 127; the sixth step for forming the low concentration P-type diffusion layer 123; the seventh step for forming the LOCOS oxide layers 111, 111a and 111b; the eighth step for forming the gate electrodes 113g, 129g and 131g; the ninth step for forming the N-type sources 113s and 131s, and N-type drains 113d and 131d; and the tenth step for forming the P-type source 129s and P-type drain 129d, whereby the count needed is found as large as ten for photolithography process steps.
It is well known that the number of photolithographic process steps have direct effects on production costs, and it is desirable, therefore, the number is decreased as much as possible. In addition, since the product cycle is becoming shorter every year, and further reduced periods for product development are required accordingly, demands for the number of the steps are increasing from these aspects, as well.
Particularly in the present case where both triple well and LOCOS offset transistor are formed simultaneously, the number of the steps is relatively large, and the reduction in the number of the process steps is of considerable importance.
Although a disclosure is found concerning the simultaneous formation of a triple well and LOCOS offset transistor (Japanese Laid-Open Patent Application No. 2000-286346), no clear statement is found on the increase in production costs and periods caused by increased number of photolithographic process steps.
In addition, another increase in the number of the steps has been encountered previously. Namely, when the LOCOS offset Pch transistor and LOCOS offset Nch transistor are formed simultaneously, extra steps are needed for forming the P-type and N-type low concentration layers (123 and 127 in FIG. 28) to surround the P-type and N-type drain, respectively, compared with the case of forming the Pch and Nch transistors. This causes the increase in the number of the steps, to thereby result in a drawback such as the increase in production costs and periods.